The present invention generally relates to semiconductor memory devices such as dynamic random access memories and static random access memories. More particularly, the present invention is concerned with a current amplifier circuit which amplifies a signal on a data bus line or an equivalence of a field effect transistor memory of a MIS (Metal Insulator Semiconductor) type, such as a MOS (Metal Oxide Semiconductor) type.
FIG. 1 is a circuit diagram of a conventional data bus signal amplifier circuit. As shown in FIG. 1, the conventional data bus signal amplifier circuit includes a data bus load circuit 1 and a data bus amplifier 2. The data bus load circuit 1 is made up of n-channel MOS transistors (hereafter simply referred to as NMOS transistors) Q1 and Q2.
The NMOS transistors Q1 and Q2 function as load elements of data buses DB and DB, and are diode-connected. The NMOS transistors Q1 and Q2 pull the data buses DB and DB up to a potential nearly equal to a high-potential power supply voltage Vcc. During a data readout operation, a sense amplifier SA coupled to bit lines BL and BL makes the potential of one of the bit lines BL and BL decrease toward a ground potential. On the other hand, a corresponding one of the NMOS transistors Q1 and Q2 functions to pull up the above-mentioned one of the bit lines BL and BL toward the power supply voltage Vcc. A readout data voltage developed between the data buses DB and DB is determined on the basis of the balance between the driving ability of the sense amplifier SA and the current supply ability of the NMOS transistors Q1 and Q2. Normally, the readout data voltage is approximately equal to 500 mV. The readout data voltage is limited to such a small voltage due to the fact that if data specified by the next address is opposite to that specified by the current address, the time necessary to reverse the data bus voltage becomes shorter as the readout data voltage becomes smaller.
Since the readout data voltage developed between the data buses DB and DB is made small, it is necessary to use an amplifier having a large voltage amplification (transconductance) ratio in order to amplify the readout data voltage. As is well known, a MOS transistor has a mutual conductance lower than that of a bipolar transistor, and does not have a large transfer ratio. However, a MOS differential circuit using a current mirror circuit functioning as a load is capable of providing a relatively high gain.
The data bus amplifier 2 is composed of p-channel MOS transistors (hereafter simply referred to as PMOS transistors) Q7, Q8, Q9 and Q10, and NMOS transistors Q3, Q4, Q5, Q6 and Q11. The PMOS transistors Q7 and Q8 form a current mirror circuit, and the PMOS transistors Q9 and Q10 form a current mirror circuit. The NMOS transistors Q3 and Q4, which are voltage amplification drive transistors, form a differential amplifier circuit to which a load consisting of the current mirror PMOS transistors Q7 and Q8 is connected. Similarly, the NMOS transistors Q5 and Q6, which are also voltage amplification drive transistors, form a differential amplifier circuit to which a load consisting of the current mirror PMOS transistors Q9 and Q10 is connected. The two pairs of the differential amplifier circuits connected in parallel form are provided to obtain differential output signals OUT1 and OUT2 from the drains of the NMOS transistors Q4 and Q5, respectively. As the transistor pairs Q3 and Q4 form the differential amplifier circuit, and the transistor pair Q5 and Q6 form the differential amplifier circuit, it is possible to obtain complementary output signals by means of a single differential amplifier circuit. However, such complementary output signals do not have good symmetry because the NMOS transistors Q3 and Q6 which respectively extract the gate voltages of the current mirror circuits have small amplitudes and generate deteriorated output signals, as compared with the NMOS transistors Q4 and Q5. The output signals OUT1 and OUT2 are drawn from the opposite sides of the two differential amplifier circuits. The NMOS transistor Q11 is provided for preventing a current from passing through the data bus amplifier 2 during a time the data bus amplifier 2 is not generating the output signals OUT1 and OUT2. When a clock .phi..sub.EN is maintained at a high level, the NMOS transistor Q11 allows the NMOS transistors Q3-Q6 to operate. On the other hand, when the clock .phi..sub.EN is maintained at a low level, the NMOS transistors Q3-Q6 are disconnected from the ground which functions as a low-potential power supply voltage.
It will be noted that C1 and C2 are parasitic capacitors coupled to the output side of the amplifier circuit, and Qa and Qb are NMOS transistors for use in column select. A column select signal Y is applied to the gates of the NMOS transistors Qa and Qb. A one-transistor one-capacitor type memory cell MC is connected to one of the bit lines (bit line BL in FIG. 1), and selected through a word line WL.
As has been described above, the conventional current mirror load type amplifier shown in FIG. 1 has a limited readout data voltage approximately equal to 500 mV, and is thus designed to pass large amounts of currents (equal to approximately 100 .mu.A-200 .mu.A) through the NMOS transistors Q3-Q6, so that they are used in a state where increased mutual conductances gm thereof are obtained. Thus, the conventional amplifier consumes a large amount of power. In addition, when a large number of amplifiers are simultaneously driven in parallel form, a large amount of IR drop occurs at the Vcc power supply line and ground line.
The PMOS transistors Q1 and Q2 function to limit the readout data voltage, and thus waste currents passing through these PMOS transistors Q1 and Q2. The NMOS transistors Q3-Q6 function as voltage amplifiers (voltage inputs and voltage outputs) which amplify the limited readout data voltage, and are thus required to have large mutual conductances gm. However, MOS transistors are not inherently optimal elements which satisfy the above-mentioned requirement.